Analog-to-digital converter

ABSTRACT

An analog-to-digital converter adapted for use in a recording system for measuring and indicating engine life usage and providing analog data representative of engine temperature and engine rpm, the summing analog data and converting the information into serial digital form to antilog to the base 2, integrating by counting and displaying the total count as an indication of percent engine life used.

United States Patent Lang ANALOG-TO-DIGITAL CONVERTER 3,569,953 3/1971 Shuda et al. ..340/347 AD 7 I t Walter T. Lan Jackson Hei hts, 2] men or 8 Primary Examiner-Thomas A. Robmson AttorneyEdwin E. Greigg [73] Assignee: Simmonds Precision Products, Inc.,

Tarrytown, N.Y. 57 ABSTRACT [22] Filed: 0 An analog-to-digital converter adapted for use in a [21] Appl. No.: 78,482 recording system for measuring and indicating engine life usage and providing analog data representative of Related ll' Data engine temperature and engine rpm, the summing [62] Division of No 791,897 Jan 17 1969 analog data and converting the information into serial P 3,593,012 digital form to antilog to the base 2, integrating by counting and displaying the'total count as an indica- 521 US. Cl ..340/347 AD tion of Permt engine life used- [511 Int. Cl. ..H03k 13/17 [58] Field of Search ..340/347 AD; 307/317 [56] References Cited 6 Claims, 6 Drawing Figures UNITED STATES PATENTS 3,445,840 5/1969 Carlstead ..340/347 AD l8 CHANNELS (I PER OCTAVE} EE E L VOLTAGE DETECTOR COUNTDO/IN SIGNAL UOTOR SEOIM A GA REE VOL as TES so iii sz iiiii n 86 ms 9 IUV G 2 .7v PER Hols OCTAVEI 4 3 2 ISOLATION INHIBIT T=.|SEC I 2 3 4 POWER GATE v SUPPLY UNBEG f" M 85% 2 u rii 83? I RUN-RESET I 1 4 STORAGE CAP 6m AW mm s? 223: M l T A G T RESET REV O2 sum RE ET m2 SIGNALS J W BRAKE 6 F (DEL 83, 6| PM 59 mass, 100 m ANN-0G TO DIGITAL T0 ANAlOG l28-256 256-5l2 GEAR L06 oouvfiguvrmrmmsik em an 952" Aw cizigiiu an gm CLOCK BINARY 00mm m H; I REv;|o% 9 PATENTED 0613 I972 3.696.400 SHEET 2 [1F 5 RATE OF LIFE USAGE PERCENT OF MAXIMUM SPEED FIG. 2

which computes and records the percent of engine life 1 which is being used for a particular engine.

It is another object of this invention to provide an engine life recorder for giving an over-speed and overtemperature indication.

Another object of this invention is to provide an engine life recorder for indicating engine start and engine running time.

It is another object of this invention to provide an engine life recorder for giving rpm output signals as well as temperature output signals.

2 It is yet another ob ect of this invention to provide an engine life recorder having an adjustment function for adjusting the rpm input parameter, the temperature input parameter and the recording rate for allowing versatile adaptation of the recorder system with different kinds of engines with which the system is employed.

I It is still another object of this invention to provide an engine life recorder with a self-test system built therein for checking the system operation from input to output without destroying any of the stored information in the system.

It is still a further object of this invention to provide an engine life recorder system which contains its own power supply and converts a DC primary power to levels compatible with the circuitry in the system.

Yet another object of this invention is to provide a recording system which is highly versatile, having high accuracy and reliability and which has provisions which remove it as a limiting factor in any engine monitoring and maintenance program.

Still another object of the invention is to provide a recording system for recording engine life usage which lends itself to easy expansion or compression of the operating dynamic range of 1,000 percent per hour up to 19,000 percent per hour.

According to one proposed embodiment utilizing the principles of this invention, there is provided a recorder system for recording engine life usage by means of a special purpose computer employing both analog and digital techniques to implement calculations. Engine rpm and engine temperature signals are accepted and combined in the recorder by means of analog circuitry. These combined signals are passed by means of a log converter and integrator which converts the information to digital circuitry to the antilog to base 2 which permits manipulations utilizing digital techniques. This allows the system to operate over a wide dynamic range to within a 5 percent accuracy. The digital signal from the log converter and integrator drives a permanent magnetic stepper motor which is geared to a digital counter for indicating percent engine life used. The

' stepper motor offers storage capabilities when deenergized, it remains in place and when energized, the motor will advance only when pulsed. When overspeed or over-temperature conditions are detected, appropriate miniature indicator flags are pulsed and magnetically latched. The over-speed or over-temperature indication will then remain fixed until externally reset.

An engine start counter is advanced every time the engine temperature exceeds a given value in Fahrenheit degrees. A comparator amplifier in the temperature channel is used to detect this given value condition and thus generates a pulse to advance the counter. At the same time an engine running time in- 5 dicator is energized and this running time is then recorded.

The rpm and temperature output signals are 0 to 5 VDC signals and are supplied externally through low output impedance amplifiers.

The delineation of the rate of life usage (RLU) is logarithmic. This gives a linear characteristic to the effect of speed and provides for a very large dynamic range. Under given temperature and speed conditions, the rate of life usage (RLU) may be expressed as: Log

5 RLU=f( T A(%S) where f(T is the log RLU applying at percent rpm; %S is the speed above 85 percent, and A is the slope of the line representing the function T The function of the logarithmic converter is to convert the analog data received as flT and A(%S) into RLU, expressing the analog sum in serial digital form and then integrating by counting. The voltage sum is converted into pulses. The higher the voltage, the greater the number of pulses in a given time period. These pulses drive a counter by means of a stepping motor and since the counter accumulates counts at a rate dependent upon the rate of engine life usage, the number displayed on the counter at any given time is the percentage of engine life used up to that time.

BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a schematic diagram of an engine life recorder system according to this invention;

FIG. 2 is a graph showing the rate of life usage in percent per hour to the variables, temperature and per cent of maximum speed;

FIG. 2a is a graph showing the computation of a slope-intercept equation Y mx b for a given temperature line shown in FIG. 2;

FIG. 3 is a schematic diagram of the rpm channel of the recorder system;

FIG. 4 is a schematic diagram of the temperature channel of the recorder system; and

FIG. 5 is a schematic diagram of the logarithmic converter and integrator circuit.

GENERAL DESCRIPTION Referring now to the block diagram shown in FIG. 1 of the overall system according to this invention, it will be seen that an rpm signalderived from appropriate transducer means connected to an engine under test, not shown, is taken through a signal conditioner l as a first step in producing a zero to 5 VDC rpm output signal. The conditioner 1 converts varying frequency signals to proportional DC signals. Since the input signal frequency is directly proportional to rpm, no additional linearization is necessary, and since the output from the signal conditioner is at a low level, the signal is taken through an output amplifier 10 which raises its level appropriately and acts as a buffer providing the desired output impedance.

The rpm signal conditioner 1 output is also fed to an over-speed circuit 11, namely, a DC analog voltage limit detector which gates out a signal whenever the signal conditioner output is at or above a preadjusted level. When gated out, the over-speed circuit 11 drives a latching flag 12 to its warning position. The flag stays latched in its warning position after the signal drops below the warning level and even after the recorder power is removed, since it is latched in place. An externally accessible re-set button may be provided to release the flag to its unlatched position.

As will be explained below, the signal conditioner also supplies the signal for driving an engine life usage counter 9.

The input signal from a temperature sensing device, such as a pyrometer or the like, not shown, is fed through a second signal conditioner 2 as a first step in producing a to volt DC temperature output signal. The signal conditioner 2 is a DC converter with a builtin function generator, the latter serving as a linearizer since the EMF of the input signal is not linearly related to temperature. The conditioner 2 is provided with a lead circuit and, in addition, uses the thermistor signal from the temperature sensor to correct for the ambient temperature of the pyrometer, to be more fully explained below. This signal conditioner output at a relatively low level is taken through an output amplifier 19 for providing the desired output level and impedance. The temperature signal conditioner output is taken through an over-temperature circuit 17, for example, a limit detector, to an over-temperature latching flag mechanism 18 to provide the over-temperature flag display. This function is identical to that described for the over-speed tlag 12 above. The DC output from the signal conditioner 2 is also taken through another limit detector and into the engine start circuit 14. The preadjusted DC level of this circuit corresponds to the equivalent of 600F. at the temperature sensor. Whenever engine temperature exceeds this point, the start circuit gates out a signal to the engine time counter and to the engine start counter 16, as shown. The latter adds one count to its display whenever the engine temperature rises through 600F. The time counter is turned on and stays on until the temperature falls below 600F. or recorder power is removed, recording engine running life. cumulatively.

The two signal conditioners 1 and 2 are disconnected from the input signals when a test switch is actuated, connecting them in turn to pre-set simulated signals. At the same time, the output displays are locked into their previous count. The two DC output signals from amplifiers l0 and 19 will indicate the pre-set simulated values and a mechanical rotating target, not shown, will show that the recorder is operating. Releasing the test switch restores the recorder to normal operation.

The two signal conditioners 1 and 2 also provide the signals which, through a process involving analog and digital computations (blocks 3-9) cause the engine life usage counter 9 to display the appropriate percent life used. Briefly, the analog signals from the signal conditioners 1 and 2 are summed, giving an analog signal related to the instantaneous rate of engine life being used. This signal is passed through a digital log converter 6 with a very wide dynamic range. The converter 6 produces a pulse train whose total pulse count is proportional to the antilog of the analog instantaneous rate usage signal. This variable count pulse train is repeated almost 1,000 times a second (although slower sampling rates can be used) and fed to a digital integrator 7. The total number of counts accumulated is directly proportional to the percent engine life used. The integrator 7 supplies pulses at a much reduced rate, but still proportional to the counter drive 8 which, in turn, actuates the display counter 9. The counter 9 constantly advances when the engine is operating and accumulates a count indicating percentage engine life used.

Referring now to FIG. 2, there is shown a graph of the rate of life usage (RLU) which relates the variables, target temperature (T and percent of maximum speed (%RPM) to the rate of life in percent per hour. The curves labeled target temperature T are each straight lines, or at least appear to be since they do not deviate from a straight line by more than the line width. The assumption that the curves T are straight lines as depicted on a semi-log graph permits the computation to be implemented by the slope intercept equation y mx b. The log of rate of life usage (log RLU) is then the linear function y. The slope of a particular T line is m, and x is S, the speed above percent RPM (S RPM-85) and b is the intercept of that T line ex pressed in the same manner as y. For a given typical graphed line of T then:

This is shown in FIG. 2a.

On this basis, the following approach can be taken. A voltage proportional to T can be added to another voltage proportional to %S, the latter having first been multiplied by a value proportional to slope. The voltage sum is then linearly related to log RLU. If the signal is then passed through a log converter, the output will be the appropriate rate signal. Integrating and displaying the signal would then provide the desired output. This approach requires only that the slope and intercept values be known, and they can be determined solely by knowing the values of T and %S.

Using graphical methods, the slopes of the T lines have been found to vary over a range of 10 percent with lower temperatures generally having higher slopes. The slopes are almost identical within region A, shown in FIG. 2a. It is possible, then, to implement a mathematical expression in which the slope would be a variable, a function of temperature. For example:

(f2) r) )+f1 r) It will be seen that f (T decreases for increasing values of T A reciprocal function can be obtained by using the circuitry of a regulated power supply whose output is controlled in a feedback network using the difference between T and a reference voltage. T would first be reshaped appropriately with a function generator. The shaping of the function generator to produce the function f would be different from that of the function f,, and the function f must be continuous. Although the graph of FIG. 2 shows lines at 50F intervals, the recorder must be able to compute the RLU for any value of temperature (or rpm) within the stated limits. It is desirable that a fixed value of slope be used so that a slope can be selected to introduce the minimum error for all values relating to region A, as shown in FIG. 2a. It is possible, then, to select slightly different intercepts for some of the graphed lines, so that the fixed slope technique would introduce only a minor error.

The intervals between intercepts of the T lines on the 85 percent RPM axis are not uniform on a linear scale. Inspection of the variation in the length of the intervals does not disclose a simple formula that could be used to implement the relationship. Here, again, the equation must be continuous for all required values of T A fixed value for the intervals between intercepts would introduce error. However, the implementation of a variable value is not difficult since the point of intercept constantly increases as the value of T increases. Accepting that the lines are parallel, then the temperature appears in the equation only once, that is, Log RLU A (%S) f (T The temperature signal is an EMF signal, non-linear with respect to temperature, and it too constantly increases with T Since the EMF would have to be passed through a function generator to be linearized, it can just as well be converted to the somewhat non-linear function that defines the intercepts.

As will be seen from FIG. 2, the liens for 1,450F and l,500F do not intersect 85 percent RPM. Estimates can be made for these values which are necessary to compute any intersections of rpm and temperature occurring in the lower right hand corner of region A.

Possible combinations of rpm and temperature intersecting to the left of or below region A (see FIG. 2a) could result in the generation of voltages equivalent to measurable values of RLU. Since these values are not to. be recorded, the circuitry will provide recording cutoff signals when RLU drops to some level below 0.06

percent per hour or when the RPM drops below 85 percent.

It is possible that the graph shown in FIG. 2 may change so long as the general form is adhered to. Thus changes in the recording rate uniformly throughout the range would involve a vertical scale shift. Changes can be made with respect to the intervals between intercepts. This is a scale factor change and is accomplished by adjusting the output of the temperature channel with respect to its input. Further changes in the slope of the lines may be effected by adjusting the output of the rpm channel with respect to its input. In addition, it is possible to change the slope as a function of temperature.

7 RPM CHANNEL FIGS. 3-5 refer to the detailed description of the cirtechnique used is the generation of a fixed width pulse which is repeated at a rate proportional to the input frequency and then integrated to develop the DC voltage. The RPM channel also contains circuitry for sensing and displaying the over-speed condition as above-referred to, developing a DC voltage proportional to RPM which is to be used externally, and detecting when RPM falls below 85 percent to inhibit a gate to a stepper motor in the log converter and integrator circuit.

As shown, the input signal is coupled by transformer 20 to ensure the required isolation. Clipping diodes 22 are provided for protecting the zero-cross detector 24 for the signal amplitude range of 0.75 volts to 10 volts peak-to-peak. The zero-cross detector 24 accepts the varying frequency, varying amplitude signal i.e., the RPM signal) and converts it to a fixed amplitude varying frequency signal which is compatible with the micro-electronic logic circuits to be discussed below. This signal is then converted to a DC voltage proportional to it in the manner indicated below.

The .IK flip flop 26 produces the fixed amplitude, fixed, that is, with width pulse which is repeated at a rate proportional to input frequency. The JK flip flop 26 is normally held in the 0 state because of the logical combination on the .l and K inputs of the signals from the zero-cross detector 24 and the binary counter circuit 28. The crystal controlled clock 30. is free running but has no effect on the binary counter 28 since it isheld in a DC preset by the JK flip flop 26.

When a zero-cross is detected the logical combination changes on the J and K inputs. The clock pulse following this causes the flip flop 26 to change state. This, in turn, releases the binary counter 28 and the count-up begins. The flip flop 26 will remain in the new state until the counter 28 reaches its full count and the control line from the counter causes the logical combination on the J and K inputs to change. The clock pulse following this will cause the JK flip flop 26 to reset to its original state completing the pulse to the integrator 32 and inhibiting the counter until the next zero-cross detection occurs, at which time the cycle is repeated. These fixed width, fixed amplitude pulses from the JK flip flop 26 are then integrated, generating a DC level. Using this technique the pulse width will always be within one clock pulse. The clock rate selected gives a resolution of 0.1 percent for the pulse width.

In addition to converting the frequency to voltage for use within the engine life recorder, the RPM channel also develops a O-S VCD signal for use outside the device. This is done by feeding the output from the integrator 32 to an output amplifier 10 (see FIG. 1). The amplifier 10 will not load the integrator 32 and will present a low output impedance for any external equipment which might be used.

The over-speed indication is accomplished by monitoring the DC output of the integrator 32 with a comparator amplifier 36. When the DC signal voltage is equivalent to 101.2% 10.2%, as shown, the comparator output will switch, pulsing the over-speed flag 12 through the flag driver mechanism 38. The flag will continue to indicate that an over-speed condition has occurred until externally reset by the application of a reset pulse from an over-speed reset switch 40.

The integrator 32 is powered by a precision variable power supply 42 which can be used to correct the various slopes of the curves represented in FIG. 2 with the addition of a slope detection, circuit 46. When a new slope requirement is detected, the amplitude of the pulse is varied accordingly to effect the change. This range of adjustment will allow l/3:3 variation of the slopes on the curve depicted. Further, an percent detector 48 will sense the output of the integrator 32.

Thus, if the voltage output represents less than 85 percent speed, the detector 48 will generate an inhibit signal stopping any information to the stepper in the log converter circuit 6 (see FIG. 1). This ensures engine life usage recording for the conditions represented by the graph shown in FIG. 2.

The Kl relay shown in FIG. 3 is the test relay. Thus, when the test mode is selected, K1 switches the input of the zero-cross detector 24 to the test signal 44. The test frequency is preselected to a value which will give a known RPM indication.

TEMPERATURE CHANNEL Referring now to FIG. 4, there is shown a detailed schematic of the temperature channel which conditions the low level temperature signals into signals compatible with the engine life recorder. This channel also senses and displays the over-temperature condition, develops a DC voltage proportional to temperature which is to be used externally, and senses and records the engine start condition by means of the engine start circuit 14 to initiate the engine running time indicator l4.

To ensure isolation the temperature channel will also be transformer coupled, as described above with respect to the RPM channel.

This is achieved by having the low level DC signal from the solar cell lead circuit 50 modulated by a solid state chopper 52, then transformer coupled by means of transformer 54 and demodulated back to DC by a second solid state chopper 56. The signal is then applied to a function generator 58 to develop the function of temperature (F to be used in the computation for per cent of engine life usage.

As shown, the temperature channel also includes two comparators 60, 62, one to detect the 1,700 signal and one to detect the 600 signal, as shown. When the signal reaches l,700 17, the comparator 60 activates the over-temperature magnetic latching indicator flag 18 by means of the flag driver mechanism 64.

The flag 18 will stay set until externally reset by the over-temperature reset switch 66. Comparator 62 detects the 600 signal and, in turn, initiates the mono 68 to advance the engine start counter 16 by means of the driver mechanism 70. The mono 68 also energizes the engine running time recorder 15 by means of the driver mechanism 72 through the SR flip Hop 74, the latter having its S input connected to the mono 68 and its R input connected to a mono 76.

The signal f (T which is nearly linear, is the signal which in turn will be transmitted externally through the low output impedance amplifier 19 (see FIG. 1). This signal will be a -5 VDC signal proportional to the input temperature and to be used with external equipment if so desired.

When self-test is initiated, relay K2 will switch in a known millivolt signal 78 allowing checkout of the completetemperature channel and of the entire system in conjunction with the RPM test signal 44. The temperature channel may also. include an input parameter adjustment circuit 80. This adjustment will affect the interval between the intercept of each of the temperature lines T on the curves shown in FIG. 2. The adjustment will allow a range of l 3:3 according to the curves shown in FIG. 2.

8 LOGARITHMIC CONVERTER AND INTEGRATOR As shown in FIG. 5, a detailed schematic of the log converter and integrator circuit is depicted. The function of the logarithmic converter is to convert the analog data received as an f (T and A (%S) into rate life usage (RLU), expressing the analog sum in serial digital form and then integrating by counting.

The voltage sum is converted into pulses, the higher the voltage, the greater the number of pulses in a given time period. These pulses are used to drive a counter by means of a stepping motor 98. Since the counter accumulates counts at a rate dependent upon the rate of engine life usage, the number displayed on the counter at any given time is the percentage of engine life used up to that time.

In the log converter and integrator circuit shown in FIG. 5, use is made of 2 as the logarithmic base. This adapts directly to the binary system of counting, readily performed by bistable flip flops. It also simplifies the synthesizing of a log function since the mantissa of a logarithm over an octave has a much more nearly linear relation to the quantity than is true over a decade.

The following scale distribution illustrates this phenomenon:

RLU (%Hr.) OCTAVE l9,000%/hr (Max. RLU) 13107.2 18 6553.6 17 3276.8 16 l638.4 15 819.2 l4 409.6 13 204.8 12 102.4 11 51.2 -10 25.6 -9 12.8 s 6.4 7 3.2 6 1.6 5 .8 4 .4 3 2 2 1 -1 -.06%/Hr (Min. RLU) .05

Like common logarithms, logarithms to base 2 have a characteristic which is integral and a mantissa which is less than 1. The characteristic indicates the order of octave number N of the next lower octave and the mantissa is the log of the ratio of the number to that value. This ratio obviously always lies between one and two and its logarithm lies between 0 and 1. Thus, in the scale illustrated above for RLU 0.5, which falls in the 0.4 to 0.8 octave, the characteristic would be 3 and the mantissa would be log 2(.5/.4) or 0.3219. According to the computer of this invention, the mantissa and characteristic are handled separately, as will be seen with reference to FIG. 5 in which is shown a block diagram of the log converter and integrator circuit.

As shown in FIG. 5, incoming analog voltage signals off (T and A (%S) to proper scale are combined at the added 5 (see FIG. 1) and stored in the storage capacitor 82. During the computing cycle, the incoming signal line is disconnected so that any change in level will not interfere with the scanning process. A l M Hz clock pulse provides the time base for the measuring system, as shown. Count-down binaries and gates are provided, as shown, so that a 256 microsecond measurement cycle is initiated every 512 microseconds. Thus nearly 2,000 determinations are made every second. During the period when measurement is not being made, the storage capacitor is connected to the signal source. Additional count-down binaries are provided, as shown, to give testing and calibration frequencies and for slewing the step motor 98.

The measurement cycle has two portions, each 128 microseconds long. The first half produces a pulse count from the converter 81 that is proportional to-the lower end of the octave in which the RLU lies. The second half produces a pulse count proportional to the point at which RLU is above the lower end of the octave. For example,

The first two columns, with the exception of the numbers enclosed in the block are taken from the scale distribution by octaves listed above. The value of 0.5 RLU is one assumed for explanatory purposes.

The analog voltages from the analog to log converter 83 are summed at the adder 84 and will be proportional to the linear progression indicated by the column headed Octave. A voltage proportional to 3% would correspond to an RLU of 0.5 and should produce a pulse count total of 50. In the first portion of the measurement cycle the converter 81, 83 (see 6 in FIG. 1) would determine that the voltage proportional to log RLU lay between the top and bottom of the third octave. Consequently, in that first portion (128 microseconds long) 40 pulses would issue from the converter 6 to the digital integrator 7 (see FIG. 1), but would stop when the pulse count was indicative of the distance above the bottom of the octave occupied by the RLU. In the illustration, one quarter above the bottom of the octave would give one quarter of the pulses associated with the bottom of the octave. The total pulse count 50 is then directly proportional to the RLU.

According to the principles of this invention, a unique technique is used to produce a pulse rate proportional to the RLU. The clock signal can be fed into a signal countdown divider 86 at any one of 19 different levels. The clock signal is then divided down by a number depending on the level at which it is inserted. For example, at the start of the first portion of the measurement cycle, the analog-to-log converter 83 has no output so that the signal proceeds without change through the second adder 84 to the voltage comparator 88 which has a series of equally spaced voltage reference steps, as shown, each corresponding to one octave on the RLU scale as above described. A coincidence detector 90 at each step occupies one state when the signal is less than the corresponding value and another state when it is more. A series of such detector gates then detects the one zone (i.e., octave) where a transition of states of the coincidence detector occurs. The particular detector gate so actuated operates a corresponding count-down selector gate 92 from a corresponding group of such count-down selector gates which then switches the serial pulse signal into the proper injection point in the signal count-down divider 86 to thereby provide the frequency division ratio for that octave. The division ratio which is frequency, out, divided by frequency, in, is 2" where N is the order of the octave involved. The same detector gate 90 also switches in a coincidence trigger module 94 which emits a pulse when the signal reaches a value equal to that of the lower boundary of the octave.

At the start of the second portion of a measurement cycle, an analog staircase voltage is generated which is proportional to the count above 128 and continues to count 256. This is applied to a characterization network so that an output voltage of log (C/l28) results, as shown in FIG. 5. Symbol C denotes the number of counts elapsed since the beginning of the staircase voltage and the quantity C/ 128 always lies between 1 and 2. Therefore, the log thereof goes only from 0 to l and characterization is relatively simple. As shown in FIG. 5, this voltage is applied subtractively to the incoming signal summation at adder 84. Since the voltage scale factor is the same for all items, voltage across the voltage comparator 88 is:

The above decreases in value as count continues. Each count simultaneously enters the count-down binary input until the above expression attains a zero value, at which time it is gated off by the coincidence trigger 94. Then,

N-[f(T A(%S)]+log (C/ l 28) 0 Transposing and substituting log N and 128 2 flT +A(%S) log (C X 2") and since 0.05 is the RLU reference axis:

RLU/0.05 antilog UIT X A(%S)] C X 2 The above process is repeated every 512 counts of the clock pulse generator. The average frequency F entering the countdown binary is then:

Selection of the entry point into the count-down binary as previously described is such that the output frequency F is:

in/2) Then,

' ya a For the maximum value of RLU (l9,000%/Hr.), F is 362.4 KB which is beyond the range of step motors. It

is counted down by 2 to [76.9 H; which allows operation of the step motor 98 well up on itstorque-speed FOULX characteristic. Its speed will be 2,654 RPM at this maximum rate. Motor 98 requires that the pulses be applied to its 4 terminals in cyclic order and this is ,accomplished by the motor sequence gates 99. The length of pulse duration is very long at low values of RLU, and a timing network limits the motor pulses to approximately 0.1 second, thus conserving power. The step motor being of the permanent magnet type retains its position even when no power is being applied. Since the motor speed is proportional to %RLU, the angular travel of its shaft is proportional to the time integral thereof or the percentage of life used. The motor drives the mechanical counter 9 as shown at a suitable gear ratio for direct readout of percentage life used. A register on the counter is provided for indications above 100 percent life since otherwise, should 100 percent be inadvertently exceeded, a much smaller and erroneous reading would be obtained.

For test purposes, a brake 100 is arranged to hold the counter stationary during the test so that data previously accumulated is not destroyed. A magnetic slip clutch 102 with no sliding parts permits the step motor to rotate under the controlled test conditions imposed. A rotary target 104 is coupled to the motor and enables motor performance to be checked with the counter stationary. For resetting the counter 9, slewing gates are provided to which signals from an external source may be applied to drive the mechanical counter in either direction. To prevent long term drift of the counter, a gate is arranged to completely deenergize the motor for inputs to the log converter 6 of less than 0.05%/Hr RLU.

It is also contemplated that double octaves may be used rather than the single octaves as above described. For this purpose the scale division boundaries will occur at 4 points instead of 2" points and the logarithmic function entering the adder 84 will then be 2 log (C/ l 28) instead of log (C128). The resulting scale distribution will now show six zones instead of 12 for the relaxed (0.06 to 100 percent) RLU range, or 10 instead of 19 for that originally required (0.06 to 19,000 percent). For example:

RLU (%/Hr.) N 52428.8 10

l9,000%/Hr. (Max. RLU in orig. spec.) l3 107.2 9 3276.8 8 8l9.2 7 204.8 6

l%/Hr. (Max. RLU in relaxed spec.) 51.2 12.8 4 3.2 3 .2 1

.06%/Hr. (Min. RLU) .05 0 Ref. RLU .05%/Hr.

The foregoing arrangement results in an economy saving by eliminating 50 percent of the voltage comparators 88, detector gates 90 and count-down selector gates 92. The number of counts for each counting interval will range from 128 to 512 instead of 128 to 256 and the counting interval is increased from 512 to 1.024 microseconds. This has no material effect on the output accuracy, as nearly 1,000 determinations are still made each second. The highly advantageous feature of counting down by binaries is still retained, and

while the number of binaries remains the same, the associated circuitry is somewhat simplified, since injection points in the counting train now occur at every other binary instead of at each binary. The above savings are made at the expense of a substantial increase in the dynamic range of the log converting function. This is divided into two portions: the digital-toanalog converter 81 (see FIG. 5) which is tripled in range since it now goes from 128 to 512 instead of 128 to 256 and the analog-to-log converter 83 whose range is extended. The function of a single octave, as above described, could be synthesized adequately by two linear segments, that is, at least two more linear segments will now be required for the log, synthesization.

It is contemplated that 8" intervals may be used instead of 4. However, the increased complexity of the log converting function would offset any gain from the accompanying reduction in the number of selector channels. Use of common logarithms (for example, log has been considered and would certainly contribute toward simplification of the system according to this invention, since common logarithms are much more in general use. The inherent simplicity, however, of binary chain division dictates the use of 2, or a power thereof, if the number of components is to be minimized. It should also be understood that logarithms of a given number to any base are linearly related to each other.

That which is claimed is:

1. An analog-to-digital converter circuit comprising:

voltage comparator means adapted to receive an input voltage,

a plurality of detector gates connected to said comparator and responsive to different values of input voltage applied thereto for generating a control effect,

means for generating a reference frequency,

a countdown divider responsive to said control effect to count down said reference frequency applied thereto in a ratio corresponding to said control effect, and gating means responsive to said reference frequency for deriving from said reference frequency an analog signal representing the logarithm of the number of pulses applied thereto and for interrupting the output pulses from said countdown divider when said analog signal attains the value of said input voltage.

2. An analog-to-digital converter circuit as set forth in claim 1, including an adder circuit means for applying to said adder circuit incoming analog voltages representative of two variable conditions of a system together with said analog signal, said input voltage being derived from the output of said adder circuit.

3. An analog-to-digital converter as set forth in claim 2, further including storage and sampling means connected to said adder for storing the incoming analog voltages during a first portion of a measurement cycle and sampling the incoming signal during a second portion of the measurement cycle.

4. An analog-to-digital converter for converting an input signal representative of two variable conditions of a system into digital signals representative of the real life usage of the system comprising, voltage comparator means adapted to receive an input voltage and having a series of voltage reference steps, coincidence detector gate connected at each step and adapted to occupy one state when the input signal is less than the reference voltage value at that reference step and another state when the input signal is more than the reference voltage value at that reference step such that one coincidence gate is actuated to detect the zone where a transition of states occurs, a corresponding group of countdown selector gates connected to the coincidence detector gates such that the particular detector gate actuated operates a corresponding countdown selector gate to count down an input reference frequency and gating means responsive to said reference frequency for deriving an analog signal representing the logarithm of the number of pulses applied thereto and for interrupting the output pulses from said countdown divider when said analog signal attains the value of said input voltage.

5. An analog-to-digital converter as set forth in claim 4, including an adder circuit, means for applying to said adder circuit the input signal representative of the two variable conditions together with said analog signal to develop said input voltage.

6. An analog-to-digital converter as set forth in claim 5, further including storage and sampling means connected to said adder circuit for a first portion of a measurement cycle and sampling the input signal during a second portion of the measurement cycle.

9 UNITED STATES PATENT OFFICE (5/69) CERTIFICATE OF CORRECTION Patent No. 3,696,400 Dated October 3, 19 72 Inventor(s) Walter I Lang It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

In the Abstract, line 4, "the summing" should read -'summing the- Col. 5, line 28, "liens" should read --lines- Col. 7, line 24, "14" should read --l5-- Col. 9, line 24, there should be a block outline enclosing this line Col. 11, line 3 9, (C128) should read (C/l28) Col. ll, line 64, "1.024" should read --l024'- Signed and sealed this 1st day of May 1973.

(SEAL) 'Attest:

EDWARD M. FLETCHER, JR. ROBERT GOTTSCHALK v Attesting Officer Commissioner of Parents P0405) UNITED STATES PATENT OFFICE (5/69) CERTIFICATE OF CORRECTION Patent No. ,696,400 Dated October 3, 1972 Inventor(s) Walter 'I. Lang Q It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

In the Abstract, line 4, "the summing" should read -summing the- Col. 5, line 28, "liens" should read --lines-- Col. 7, line 24, "14" should read -l5-- Col. 9, line 24, there should be a block outline enclosing this line Col. 11, line 39, (C128) should read (c/128) Col. 11, line 64, "1.024" should read --1024- Signed and sealed this lst day of May 1973.

(SEAL) Attest:

EDWARD M. FLETCHER, ,J'R. ROBERT GOTTSCHALK V Attesting Officer 2 I Commissioner of Patents 

1. An analog-to-digital converter circuit comprising: voltage comparator means adapted to receive an input voltage, a plurality of detector gates connected To said comparator and responsive to different values of input voltage applied thereto for generating a control effect, means for generating a reference frequency, a countdown divider responsive to said control effect to count down said reference frequency applied thereto in a ratio corresponding to said control effect, and gating means responsive to said reference frequency for deriving from said reference frequency an analog signal representing the logarithm of the number of pulses applied thereto and for interrupting the output pulses from said countdown divider when said analog signal attains the value of said input voltage.
 2. An analog-to-digital converter circuit as set forth in claim 1, including an adder circuit means for applying to said adder circuit incoming analog voltages representative of two variable conditions of a system together with said analog signal, said input voltage being derived from the output of said adder circuit.
 3. An analog-to-digital converter as set forth in claim 2, further including storage and sampling means connected to said adder for storing the incoming analog voltages during a first portion of a measurement cycle and sampling the incoming signal during a second portion of the measurement cycle.
 4. An analog-to-digital converter for converting an input signal representative of two variable conditions of a system into digital signals representative of the real life usage of the system comprising, voltage comparator means adapted to receive an input voltage and having a series of voltage reference steps, coincidence detector gate connected at each step and adapted to occupy one state when the input signal is less than the reference voltage value at that reference step and another state when the input signal is more than the reference voltage value at that reference step such that one coincidence gate is actuated to detect the zone where a transition of states occurs, a corresponding group of countdown selector gates connected to the coincidence detector gates such that the particular detector gate actuated operates a corresponding countdown selector gate to count down an input reference frequency and gating means responsive to said reference frequency for deriving an analog signal representing the logarithm of the number of pulses applied thereto and for interrupting the output pulses from said countdown divider when said analog signal attains the value of said input voltage.
 5. An analog-to-digital converter as set forth in claim 4, including an adder circuit, means for applying to said adder circuit the input signal representative of the two variable conditions together with said analog signal to develop said input voltage.
 6. An analog-to-digital converter as set forth in claim 5, further including storage and sampling means connected to said adder circuit for a first portion of a measurement cycle and sampling the input signal during a second portion of the measurement cycle. 